The present invention relates to data communication circuits. More particularly, the present invention relates to a first-in-first-out (FIFO) buffer for buffering data frames in a data communication circuit.
Data communication circuits such as network devices and telecommunications circuits typically have several communication channels for connecting to multiple devices such as workstations, telephone and television systems, video teleconferencing systems and other facilities over common data links or carriers. A channel is a logical path from one source to one destination and can be unidirectional or bidirectional. A data routing circuit, such as a direct memory access (DMA) controller, routes data to and from each channel. The data is usually grouped into frames, or packets, of any size. Each channel includes a data interface controller, such as a serial wide area network (SWAN) controller or a local area network (LAN) controller that is coupled to the data routing circuit for controlling transmission of its respective data over the data link or carrier.
Data interface controllers are often configured to transmit frames or packets of data having an arbitrary length at a fixed speed. For example, a WAN controller may transmit an Internet Protocol (IP) packet over a fixed speed Interactive Services Digital Network (ISDN) Basic Rate Interface (BRI) using high level data link control (HDLC) framing. Alternatively, a LAN controller such as an Ethernet controller may transmit an IP packet over a fixed speed 10 or 100 Mbps LAN, for example.
In these applications, it is common to use a first-in-first-out (FIFO) memory for buffering transmit and receive data between the data routing circuit and data interface controller. Each communication channel typically has its own transmit FIFO and its own receive FIFO. A typical FIFO uses a dual port random access memory (RAM) for storing the data. One port is used by the data interface controller and the other port is used by the data routing circuit. During a transmit operation, the data routing circuit writes the data packets to one end of the FIFO at a data routing circuit transmission rate, and the data interface controller reads the packets at the other end of the FIFO at the rate of the fixed speed data interface.
The FIFO is needed, because the data routing circuit transmission rate is generally substantially higher on average than the rate of the fixed speed data interface. Also, the data routing circuit is subject to xe2x80x9cgapsxe2x80x9d in its ability to feed the FIFO because of memory access latencies, contention with other master devices that are coupled to the memory bus and control logic overhead.
Each FIFO is accompanied by control logic that requests service from the data routing circuit when the amount of data in the FIFO drops below a certain point, such as an xe2x80x9calmost emptyxe2x80x9d threshold. This amount is chosen such that even with worst-case memory access latency, bus contention and control overhead, the data in the FIFO will not be completely drained by the fixed speed data interface.
The fixed speed data interface controller is typically configured to start extracting data from the FIFO only after a set amount of data is in the FIFO. This point is referred to as a xe2x80x9cstartxe2x80x9d threshold. Once the data interface controller has started transmitting, it must continue transmitting until the end of the frame. If the data interface controller is allowed to extract data from the FIFO as soon as the first bit of data is stored in the FIFO from the data routing circuit, the FIFO will have very little tolerance for data routing circuit delays that may be occasioned by memory access latency, bus contention and control logic overhead. If the FIFO runs out of data before the entire data packet or frame has been transmitted, a FIFO under run occurs which corrupts the transmission. The amount of data that needs to be in the FIFO before the fixed speed data interface controller is allowed to begin extracting data from the FIFO is calculated to accommodate the worst-case data routing circuit delays.
Similarly, during a receive operation, the data interface controller writes the data packets at one end of the FIFO at the rate of the fixed speed data interface, and the data routing circuit reads the data packets from the other end of the FIFO at the data routing circuit transmission rate. The data routing circuit waits until there is a sufficient amount of data stored in the FIFO before reading a data packet from the FIFO. This allows the data routing circuit to read an entire packet or frame from the FIFO in a xe2x80x9cburst modexe2x80x9d at the data routing circuit transfer rate. The amount of data that is required to be stored in the FIFO before the data routing circuit will start reading data from the FIFO is determined by a selected xe2x80x9cstartxe2x80x9d threshold, similar to the transmit operation.
There are two difficulties that occur with the above-described transmit and receive operations. During a transmit operation, if the last data frame being sent by the data routing circuit is not large enough to trigger the start threshold, then the data interface controller may never read the data frame out of the FIFO. Likewise, during a receive operation, when the last data frame is received by the data interface controller and stored in the FIFO, the data routing circuit will read data out of the FIFO until the start threshold flag is de-asserted. The remainder of the data frame that is below the start threshold in the FIFO may be stuck in the FIFO.
In these situations, the transmit and receive devices therefore need some way of knowing that a data frame is in the FIFO waiting to be transmitted. For example, a xe2x80x9csmartxe2x80x9d data interface controller could be-used in which the transmitting device (i.e. the data interface controller) would monitor a FIFO-empty flag provided by the FIFO and would begin transmitting if the FIFO was not empty and a certain amount of time had passed. The amount of time that the data interface controller would, wait before beginning a transmission could be based on a predetermined relationship between the data routing circuit transmission rate and the fixed speed data interface rate among other factors. Similarly, during receive operations, the data routing circuit could just read data until the FIFO was empty. However, the ability of the data routing circuit to xe2x80x9cburstxe2x80x9d data frames from the FIFO may be compromised due to an unknown amount of data in the FIFO.
The FIFO buffer of the present invention addresses these and other problems and offers other advantages over the prior art.
One aspect of the present invention is directed to a first-in-first-out (xe2x80x9cFIFOxe2x80x9d) buffer for buffering communication data. The FIFO buffer includes a write port having a data input, an end-of-frame input and a write control input, a read port having a data output, an end-of-frame output and a read control input, and a plurality of storage locations. A write end-of-frame counter is coupled to the write port and has a write count output, which increments as a function of the end-of-frame input and the write control input. A read end-of-frame counter is coupled to the read port and has a read count output, which increments as a function of the end-of-frame output and the read control input. A comparator has a first compare input coupled to the write count output, a second compare input coupled to the read count output and a compare output indicating whether there is a data frame stored in the plurality of storage locations.
Another aspect of the present invention is directed to a data communication circuit for buffering data, which is divided into multiple-bit data frames. The circuit includes a data routing circuit, a data interface, a transmit first-in-first-out (xe2x80x9cFIFOxe2x80x9d) buffer and a receive FIFO buffer. Each buffer is operatively coupled between the data routing circuit and the data interface and includes a write port having a data input, an end-of-frame input and a write control input, a read port having a data output, an end-of-frame output and a read control input, and a plurality of storage locations. A write end-of-frame counter is coupled to the write port and has a write count output, which increments as a function of the end-of-frame input and the write control input. A read end-of-frame counter is coupled to the read port and has a read count output, which increments as a function of the end-of-frame output and the read control input. A comparator has a first compare input coupled to the write count output, a second compare input coupled to the read count output and a compare output indicating whether there is a data frame stored in the plurality of storage locations.
Yet another aspect of the present invention is directed to a method of buffering multiple-bit data frames in a data communication system, wherein each data frame has a beginning and an end. The method includes storing successive portions of successive ones of the data frames in a first-in-first-out (FIFO) buffer. Each successive portion includes an end-of-frame flag, which is asserted when the portion being stored includes the end that data frame. A grey-coded write count is incremented as each of the asserted end-of-frame flags is stored in the FIFO. The successive data frame portions are read from the FIFO buffer. A grey-coded read count is incremented as each of the data frame portions that have an asserted end-of-frame flag is read from the FIFO. The step of reading is controlled as a function of a comparison of the write count and the read count.